Image sensor for mobile use and associated methods

ABSTRACT

The image sensor includes an array of pixels. Each pixel has a pinned photodiode which transfers charge via a transfer gate to a floating diffusion, from which output is provided by a source follower. Each column has a voltage supply line and a signal line. Each row has a transfer gate control line, a read/reset control line, and a read/reset voltage line which receives alternately zero volts and a predetermined positive voltage from a decoder circuit.

FIELD OF THE INVENTION

The present invention relates to solid state image sensors, and isparticularly useful in image sensors for use in mobile applications suchas cellular phones. The invention also relates to devices, such asmobile phones, digital cameras and optical pointing devices (e.g.computer mouse) incorporating solid state image sensors.

BACKGROUND OF THE INVENTION

Image sensors using pinned photodiode pixels, typically implemented inCMOS architecture, are well known. Such image sensors in manyapplications have the advantage that both the image sensitive elementand the image processing circuitry can be embodied in a single chipwhich can be manufactured using CMOS techniques.

However, there is increasing demand for image sensors for use in mobileapplications such as mobile phones where power supplies are verylimited. Specifically, as discussed in more detail below, many mobiledevices have a battery supply at 2.4V whereas prior art pinnedphotodiode image sensors require a voltage of about 3V. This can be metby providing a charge pump, but at the expense of increasing the circuitcomplexity and cost. Moreover, the charge pump will typically require astorage capacitor which is too large to be provided on-chip, and thus anoff-chip component is required.

SUMMARY OF THE INVENTION

The present invention seeks to provide an image sensor which at leastaddresses the above described problems.

The invention provides a solid state image sensor comprising an array ofpixels arranged in rows and columns, each pixel having a photodiodeconnected to a floating diffusion via a transfer gate, the floatingdiffusion providing an output to a column output line via a sourcefollower. Each row has a transfer gate control line. The image sensorincludes at least one read/reset voltage supply line connected to thefloating diffusion via a read/reset transistor. The or each read/resetvoltage supply line is driven by a decoder circuit at alternately apredetermined reset voltage and a substantially lower voltage.

The invention further provides a digital camera, a mobile telephone, anda computer pointing device, each having such an image sensor.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of exampleonly, with reference to the drawings, in which:

FIG. 1 is a schematic diagram of one pixel of a prior artfour-transistor pinned photodiode image sensor;

FIG. 2 is a schematic diagram showing a prior art image sensorincorporating an array of pixels as in FIG. 1, and showing the powersupply arrangement;

FIGS. 3 a and 3 b are schematic diagrams of one pixel an image sensoraccording to the invention;

FIG. 4 is a timing diagram showing timing in the pixel of FIG. 3;

FIGS. 5 a-5 c are schematic diagrams showing an image sensorincorporating an array of pixels as in FIG. 3;

FIG. 6 is a schematic diagram showing voltage conditions in the pixel ofFIG. 3 after reset and during readout; and

FIG. 7 is a schematic diagram illustrating an alternative embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring initially to FIG. 1, in a prior art arrangement a pixel 10 ofan image array has three horizontal lines: a reset line RST(j), atransfer gate line TG(j), and a read line RD(j), and two vertical lines:a reset voltage line VRT and a signal line Vx. However, the resetpotential of the floating diffusion FD is VRT, which is also the sourcefollower supply voltage. This causes a problem that the reset potentialof FD cannot be generated separately from the source follower supplyvoltage. In this case, VRT must supply current (typically a few mA) tobias the source followers at a sufficiently high voltage to causecomplete charge transfer from the pinned photodiode without lag;typically the required voltage is around 3V. In an image sensor formobile applications the supply voltage to the chip is often only2.4-2.5V, and thus the 3V supply must be generated from a charge pump.

Referring to FIG. 2 which shows a prior art circuit in greater detail,an array of pixels 10 is supplied at 3V at 12 from a battery supply Vddof 2.4V via a charge pump 14 and a voltage regulator 16 controlled by abandgap voltage 18. The load current required to be delivered by thecharge pump 14 determines the size of the pump capacitors, clockfrequency, and efficiency. Often this necessitates a storage capacitor20 of a size which can only be provided off-chip, which increases thesystem physical size and cost.

Referring to FIGS. 3 a and 3 b, there is shown the operating principleof a single pixel 30 in one embodiment of the present invention. Thepixel 30 operates as a pinned photodiode pixel using three transistorsM1-M3, the floating diffusion being shown as a capacitor FD. The pixel30 has vertical VRT and Vx lines, and horizontal read reset lineRD/RST(j)k and transfer gate line TG(j). The floating diffusion FD isreset to the voltage on a further horizontal line VRST(j). This voltageis time multiplexed between VRST and a much lower voltage (from zero toa few hundred mV above ground) by a Y-decoder circuit 32. FIG. 3 aillustratively shows the Y-decoder circuit 32 as an analog multiplexer.FIG. 3 b illustratively shows the circuit 32 in the form of a levelshifter.

The timing of the pixel 30 is illustrated in FIG. 4. To deactivate thepixel in row j the sensing node FD is set at 0V (or other low voltage)when the pixel is not being read, switching the source followertransistor M3 off. This is done by RD/RST(j)=0 and VRST(j)=0,rstb(j)=hi, which will set VRST(j)=0V. The transistor M2 conducts the FDto VRST(j)=0V, maintaining the source follower transistor M3 in the offstate. RD/RST(j) and rst(j) are maintained in these states by theY-decoder 32 for all rows of pixels (j) which are not being read.

To read out a row of pixels, rst(j) is asserted setting VRST(j)=VRST.Since RD/RST(j) is normally still asserted (pixel is not being readbeforehand) the FD is set to VRST by M2. The high voltage on the gate ofM3 causes current to flow producing a voltage Vx which is Vt below thevoltage on M3. All other M3 in pixels on the same column have a gatevoltage of 0V and so are not conducting.

The reset and signal voltages from the pixel are sampled by signals CDS1and CDS2 at the base of the column. The RD/RST(j) line falls to 0Vcausing charge injection and reset coupling to produce a small decreasein the voltage on FD. The voltage on Vx follows this change and issampled by CDS1 on a column capacitor. This sample is the blackreference sample from the pixel.

The signal sample from the pixel is produced by pulsing TG(j) low thenhigh to transfer charge from the pinned photodiode to the floatingdiffusion FD. This produces a variable downwards voltage swing on FDproportional to the amount of light charge integrated on the photodiode.The column voltage Vx follows the change in FD and is sampled by CDS2onto a second column sampling capacitor. The sampled voltages aresubtracted to remove kT/C noise introduced when releasing FD from reset.

It is noted that the pixel in FIG. 3 can be realized with threehorizontal lines (RD/RST(j), VRST(j), and TG(j)) and two vertical lines(VRT and Vx). Using this three transistor pixel with horizontal VRSTallows the constraints on VRT and VRST to be separated. Referring toFIGS. 5 a-5 c, VRT can be supplied directly by an input battery voltageAVDD=2.5V via a voltage regulator 34. VRST still has to be typically 3Vwhich can be produced by a charge pump 36 supplying a voltage regulator38.

The load on VRST is purely capacitive. A row of FD capacitances must becharged on the readout of each video line; this typically amounts to 3pF every 50 μs. No DC current is involved. This makes it possible to usea charge pump with on-chip components of reasonable size, typically witha storage capacitor of about 20 μF which can readily be providedon-chip.

FIG. 6 illustrates the voltage conditions on M3 during and after reset.The bias conditions on M3 make it possible for the drain voltage to belower than the gate voltage provided the Vgs drop of M3 is sufficientlylarge. Since body effect has a significant effect, the Vgs drop isaround 1V.

FIG. 7 shows an alternative embodiment, in which a number n ofphotodiode sites are coupled to a single floating diffusion FD and sharesource follower and reset transistors M3 and M2. The technique ofsharing transistors is effective in reducing the proportion ofnon-photosensitive circuitry area to photodiode area for maximum lightgathering capacity and minimum pixel size.

The invention thus makes it possible to dispense with off-chip storageelements. Further, the invention allows a pinned-photodiode arrangementwhich requires only three (or fewer) transistors per pixel. It will beappreciated that the solid state image sensor of the invention can beincorporated in a number of devices.

As one example, the sensor may form part of a digital camera in which acamera lens focuses a desired image onto the image plane of the imagesensor. In another use, the image sensor may be incorporated in a mobilephone having the customary receiving and transmitting means for digitalsignals. A further use is in an optical mouse, or pointing device, foruse with a computer. The optical mouse has a housing which provides abutton surface and which contains an illumination source, a lens, and asolid state image sensor. The lens provides optical transmission ofhighlights, produced by the illumination source on a mouse mat orequivalent to the image sensor.

The invention is particularly suited to such applications, whereefficient power supply arrangements are desirable to minimize currentdraw and battery size, and to prolong battery life.

1-14. (canceled)
 15. A solid state image sensor comprising: a pluralityof column output lines; an array of pixels arranged in rows and columns,each pixel comprising a transfer gate, a floating diffusion, a sourcefollower, and a photodiode connected to the floating diffusion via thetransfer gate, the floating diffusion providing an output to a columnoutput line via the source follower; each row of pixels including atransfer gate control line; at least one read/reset transistor; at leastone read/reset voltage supply line connected to the floating diffusionvia the read/reset transistor; and a decoder circuit alternately drivingthe at least one read/reset voltage supply line at a predetermined resetvoltage and a substantially lower voltage.
 16. A solid state imagesensor according to claim 15, wherein the substantially lower voltage isbetween zero and a few hundred millivolts above a reference voltage. 17.A solid state image sensor according to claim 15, wherein each pixelincludes a read/reset transistor and each row has a read/reset voltagesupply line.
 18. A solid state image sensor according to claim 15,wherein a plurality of pixels in a column share a common floatingdiffusion, an associated common read/reset transistor, and a commonread/reset voltage supply line.
 19. An image sensor according to claim15, wherein said decoder circuit comprises an analog multiplexer.
 20. Animage sensor according to claim 15, wherein said decoder circuitcomprises a level shifter.
 21. An image sensor according to claim 15,wherein each column line is connected alternately to a black levelbuffer and a signal level buffer synchronously with the read/resetvoltages, and the stored values are used to cancel reset (kT/C) noise.22. An image sensor according to claim 21, wherein said buffers comprisecolumn capacitors.
 23. An image sensor according to claim 15, furthercomprising a power supply circuit for supplying the decoding circuitwith the predetermined reset voltage, the power supply circuit includinga charge pump circuit and associated on-chip storage capacitors.
 24. Animage sensor according to claim 23, wherein the charge pump circuitincludes an on-chip storage capacitor having about 20 μF capacitance.25. An image sensor according to claim 23, further comprising a secondpower supply circuit for supplying power to a remainder of the imagesensor at a lower voltage than that of the charge pump.
 26. A method ofoperating a solid state image sensor comprising a plurality of columnoutput lines, an array of pixels arranged in rows and columns, eachpixel including a transfer gate, a floating diffusion, a sourcefollower, and a photodiode connected to the floating diffusion via thetransfer gate, the floating diffusion providing an output to a columnoutput line via the source follower, each row of pixels including atransfer gate control line, the sensor further comprising at least oneread/reset transistor, and at least one read/reset voltage supply lineconnected to the floating diffusion via the read/reset transistor, themethod comprising: alternately driving the at least one read/resetvoltage supply line at a predetermined reset voltage and a substantiallylower voltage.
 27. A method according to claim 26, wherein an analogmultiplexer drives the at least one read/reset voltage supply line. 28.A method according to claim 26, wherein a level shifter drives the atleast one read/reset voltage supply line.
 29. An electronic devicecomprising: a solid state image sensor including an array of pixelsarranged in rows and columns, each pixel comprising a transfer gate, afloating diffusion, a source follower, and a photodiode connected to thefloating diffusion via the transfer gate, the floating diffusionproviding an output to a column output line via the source follower,each row of pixels including a transfer gate control line, at least oneread/reset transistor, at least one read/reset voltage supply lineconnected to the floating diffusion via the read/reset transistor, and adecoder circuit alternately driving the at least one read/reset voltagesupply line at a predetermined reset voltage and a substantially lowervoltage.
 30. An electronic device according to claim 29 wherein thedevice comprises a digital camera.
 31. An electronic device according toclaim 29 further comprising a receiving and transmitter for digitaldata; the receiver, transmitter and image sensor defining a mobiletelephone.
 32. An electronic device according to claim 29 furthercomprising a housing having a button surface, a source of illuminationmounted within the housing, and the solid state image sensor mountedwithin the housing and optically coupled by a lens to highlightsoriginating from the illumination source; the housing, illuminationsource, lens and image sensor defining a computer system pointingdevice.